1. Field of the Invention
The present invention relates to a semiconductor device and a method of operating thereof, and particularly, the present invention relates to a semiconductor device having a circuit, which is used for a memory, and a method of operating thereof.
2. Description of Related Art
A semiconductor integrated circuit having a memory such as a dynamic random access memory (DRAM) integrated therein has been known. In recent years, in response to the demand of low power consumption, a semiconductor integrated circuit is progressing in lowering of a power source voltage. In response to the demands of this, an embedded DRAM also is progressing in lowering of a power source voltage. However, as lowering of a power source voltage progresses, a threshold voltage of an MOS transistor comes close to a power source voltage, so that there is a possibility that a fast read of the embedded DRAM is difficult. As a technique dealing with this, a DRAM with a ground-precharge configuration has been known.
For example, Japanese Laid-Open Patent Application JP-P2004-265533A (corresponding to U.S. Pat. No. 6,914,840(B2)) discloses a semiconductor memory circuit. FIG. 1 is a circuit diagram showing a semiconductor memory circuit of JP-P2004-265533A. This semiconductor memory circuit 101 includes a memory cell 102, a dummy cell 104, a precharge circuit 108, and a sense amplifier 106. The memory cell 102 includes a first capacitor 111 and a first transistor Qc. The first capacitor 111 accumulates electric charges corresponding to memory data. The first transistor Qc is connected to a word line WL at a gate, is connected to a first bit line BT at one of source/drain regions, and is connected to a first capacitor 111 at the other of the source/drain regions. The dummy cell 104 includes a second capacitor 112, a second transistor Qr1, and a third transistor Qr2. The second capacitor 112 has a smaller capacitance than that of the first capacitor 111. The second transistor Qr1 is connected to a dummy word line WR at a gate, is connected to a second bit line BN at one of source/drain regions, and is connected to a second capacitor 112 at the other of the source/drain regions. The third transistor Qr2 electrically connects the second capacitor 112 to a voltage line WRP supplying a first voltage in response to a precharge signal when the dummy word line WR is inactive. The precharge circuit 108 precharges first and second bit lines BT and BN to a second voltage when the word line WL and the dummy word line WR are inactive. The sense amplifier 106 detects a potential difference between the first and second bit lines BT and BN when the word line WL and the dummy word line WR are activated and the first and second capacitors 111 and 112 are electrically connected to the first and second bit lines BT and BN, respectively. Then, the sense amplifier 106 amplifies voltages of the first and second bit lines BT and BN to the first and second voltages or the second and first voltages, respectively, when the sense amplifier 106. All of the transitions from an inactive voltage level into an active voltage level of the word line WL and the dummy word line WR are directed from the second voltage to the first voltage.
FIG. 2 is a timing chart showing an operation of the semiconductor memory circuit of JP-P2004-265533A. It is perceived that this semiconductor memory circuit is operated as follows. During a precharge period (as well as before a word selection period), a precharge line PDL is activated (VDD), and the first and second bit lines BT and BN are precharged to a ground voltage by the precharge circuit 108. In addition, a voltage line WRP is activated (VPP), and the second capacitor 112 (a capacitance Cs) is charged via the transistor Qr2. After that, during the word selection period, the word line WL is activated (VPP), and electric charges of the first capacitor 111 (a capacitance CS) is supplied to the first bit line BT via the transistor Qc. As a result, in the case where the electric charges are accumulated in the first capacitor 111 corresponding to the data, a potential of the first bit line BT is BT (H). On the other hand, in the case where the electric charges are not accumulated in the first capacitor 111 corresponding to the data, the potential of the first bit line BT is BT (L): GND. In this case, the dummy word line WR is also activated (VPP), and the electric charges of the second capacitor 112 are supplied to the second bit line BN via the transistor Qr1. As a result, the potential of the second bit line BN is an intermediate potential between BT (H) and BT (L). In other words, BT (H)−BN=BN−BT (L)=ΔV is established. Here, ΔV is determined based on a [bit line capacity Cb]/Cs. After that, the sense amplifier 106 is activated (VDD). As a result, when the potential of the first bit line BT is BT(H), BT(H) is made to increase to VDD. In addition, since the potential of the second bit line BN is BN(H), BN(H) is made to decrease to GND. On the other hand, when the potential of the first bit line BT is BT(L), BT(L) remains GND. In addition, since the potential of the second bit line BN is BN(L), BN(L) is made to increase to VDD.
However, we have now discovered the following facts. According to the semiconductor memory circuit of the above-mentioned JP-P2004-265533A, it is considered that three wiring lines including the dummy word line WR for reading the dummy cell 104, the voltage line WRP for precharging, and the word line WL of the memory cell 102 need to be driven at VPP (or a voltage close to VPP>VDD: positive) that is an activated level and at VBB (negative) that is an inactivated level. A current efficiency of a power source for supplying these both voltages is low, and the percentage of the electric power thereof is forty percent or more in the entire electric power to be consumed on the read operation, which is a largest ratio item. Therefore, in the semiconductor device having the memory circuit, a technique capable of reducing the power consumption is expected.
In addition, on a read operation of the memory cell 102, a potential of BN is raised by ΔV. In this case, a limit of a low voltage operation of the sense amplifier 106 depends on whether or not the gate voltages to be applied to PMOS transistors Q1 and Q3 in the sense amplifier 106 are sufficiently high for the threshold voltage Vth of these transistors. A gate voltage to be applied in this case is (VDD−ΔV), so that (VDD−ΔV)>Vth is an operating limit of the PMOS transistors Q1 and Q3. Here, the semiconductor integrated circuit having the embedded DRAM is made to reduce the power consumption by lowering of the power source voltage VDD of a logic circuit. In this case, if the VDD is lowered, (VDD−ΔV) approaches to Vth, and this causes a danger that an operating rate of the sense amplifier 106 is lowered. In addition, if the VDD is lowered, the influence of ΔV is increased and it is danger that variation of ΔV influences stability of the operation, because ΔV is changed due to variation of Cb/Cs that is easily influenced by the production tolerance. In the semiconductor device having the memory circuit, a technique capable of stably carrying out the read operation while lowering the power source voltage is required.